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19-1523; Rev 5, 7/03
+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
General Description
The 1.25Gbps MAX3264/MAX3268/MAX3768 and the 2.5Gbps MAX3265/MAX3269/MAX3765 limiting amplifiers are designed for Gigabit Ethernet and Fibre Channel optical receiver systems. The amplifiers accept a wide range of input voltages and provide constantlevel output voltages with controlled edge speeds. Additional features include RMS power detectors with programmable loss-of-signal (LOS) indication, an optional squelch function that mutes the data output signal when the input voltage falls below a programmable threshold, and excellent jitter performance. The MAX3264/MAX3265/MAX3765 feature current-mode logic (CML) data outputs that are tolerant of inductive connectors and a 16-pin TSSOP package, making these circuits ideal for GBIC receivers. The MAX3268/ MAX3269/MAX3768 feature standards-compliant positive-referenced emitter-coupled logic (PECL) data outputs and are available in a tiny 10-pin MAX package that is ideal for small-form-factor (SFF) receivers.
Features
o +3.0V to +5.5V Supply Voltage o Low Deterministic Jitter 14ps (MAX3264) 11ps (MAX3265/MAX3765) o 150ps (max) Edge Speed (MAX3265/MAX3765) 300ps (max) Edge Speed (MAX3264) o Programmable Signal-Detect Function o Choice of CML or PECL Output Interface o 10-Pin MAX or 16-Pin TSSOP Package
Ordering Information
PART MAX3264CUE MAX3264C/D MAX3265CUE MAX3265CUB MAX3265C/D MAX3265EUE MAX3268CUB MAX3268C/D MAX3269CUB MAX3269C/D MAX3765CUB TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 16 TSSOP-EP Dice* 16 TSSOP-EP 10 MAX-EP Dice* 16 TSSOP-EP 10 MAX-EP Dice* 10 MAX-EP Dice* 10 MAX-EP
Applications
Gigabit Ethernet Optical Receivers Fibre Channel Optical Receivers System Interconnect ATM Optical Receivers
Selector Guide appears at end of data sheet. Pin Configurations appear at end of data sheet.
MAX3768CUB 0C to +70C 10 MAX-EP *Dice are designed to operate from 0C to +70C, but are tested and guaranteed only at TA = +25C. EP = Exposed paddle.
Typical Operating Circuits
CAZ VCC VCC VCC
CAZ1
CAZ2
CIN 0.01F IN+ 100 IN-
MAX3264CUE MAX3265CUE MAX3265EUE
OUT+
RTERM 0.01F
OUT-
0.01F
RL 100
MAX3266 MAX3267
CIN 0.01F TH SQUELCH LOS LOS LEVEL VCC RTH N.C. LOSS OF SIGNAL N.C. N.C.
RTERM
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ............................................-0.5V to +6.0V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at SQUELCH, CAZ1, CAZ2, LOS, LOS, TH..................................-0.5V to (VCC + 0.5V) Voltage at LEVEL...................................................-0.5V to +2.0V Current into LOS, LOS ..........................................-1mA to +9mA Differential Input Voltage (IN+ - IN-) .....................................2.5V Continuous Current at CML Outputs (OUT+, OUT-) ..........................-25mA to +25mA Continuous Current at PECL Outputs (OUT+, OUT-) .........50mA Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 27mW/C above +70C) .........2162mW 10-Pin MAX (derate 20mW/C above +70C) ...........1600mW Operating Ambient Temperature Range .............-40C to +85C Storage Temperature Range .............................-55C to +150C Processing Temperature (dice) .......................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Data outputs terminated per Figure 1, VCC = +3.0V to +5.5V, TA = 0C to +70C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Data Rate Input Voltage Range Deterministic Jitter Random Jitter CONDITIONS MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 (Notes 2, 3) MAX3265/MAX3269/MAX3765 (Notes 2, 3) MAX3264/MAX3268/MAX3768 (Notes 2, 4) MAX3265/MAX3269/MAX3765 (Notes 2, 4) MAX3264 (Note 5) Data Output Edge Speed MAX3265/MAX3765 (Note 6) MAX3268/MAX3768 (Note 5) MAX3269 (Note 6) LOS Hysteresis LOS Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level (Notes 2, 7) (Notes 7, 8) RTH = 2.5k RTH = 2.5k MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 1.20 2.20 2.5 80 80 5 10 14 11 15 8 175 100 150 100 4.4 1 2.6 4.8 4.5 8.5 300 150 300 150 dB s mV mV ps MIN TYP 1.25 2.5 1200 1200 30 25 MAX UNITS Gbps mV psp-p psRMS
2
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(Data outputs terminated per Figure 1, VCC = +3.0V to +5.5V, TA = 0C to +70C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Medium LOS Assert Level Medium LOS Deassert Level High LOS Assert Level High LOS Deassert Level Squelch Input Current Differential Input Resistance Input-Referred Noise CML Output Voltage PECL Output High Voltage PECL Output Low Voltage LOS Output High Voltage LOS Output Low Voltage Output Signal When Squelched Power-Supply Rejection Ratio Low-Frequency Cutoff Output Resistance (Single Ended) IN+ to INMAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 LEVEL = open, RLOAD = 50 LEVEL = GND, RLOAD = 75 Referenced to VCC Referenced to VCC ILOS = -30A ILOS = +1.2mA Outputs AC-coupled f < 2MHz CAZ = open CAZ = 0.1F MAX3264/MAX3265/MAX3765 MAX3268/MAX3269/MAX3768 MAX3268 MAX3269 MAX3264 Power-Supply Current Figure 2 Output not squelched Output squelched MAX3265 MAX3765 MAX3768 MAX3765 85 20 20 2 2 100 4 39 48 38 50 50 39 64 62 78 62 76 76 62 90 mA 115 550 1100 -1.025 -1.810 2.4 0.4 1270 RTH = 7k RTH = 7k RTH = 20k RTH = 20k CONDITIONS MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 0 97 9.4 18.0 MIN 5.6 9.9 TYP 9 16 15 27 21.6 41.5 35 67 80 100 150 230 1200 1800 -0.880 +1.620 400 103 19.8 40.5 MAX UNITS mV mV mV mV A VRMS mV V V V V mV dB MHz kHz
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
ELECTRICAL CHARACTERISTICS--MAX3265EUE
(Data outputs terminated per Figure 1, VCC = +3.0V to +5.5V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Data Rate Input Voltage Range Deterministic Jitter Random Jitter Data Output Edge Speed LOS Hysteresis LOS Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level Medium LOS Assert Level Medium LOS Deassert Level High LOS Assert Level High LOS Deassert Level Squelch Input Current Differential Input Resistance Input-Referred Noise CML Output Voltage LOS Output High Voltage LOS Output Low Voltage Output Signal When Squelched Power-Supply Rejection Ratio Low-Frequency Cutoff Output Resistance (single ended) Power-Supply Current Figure 2 LEVEL = open, RLOAD = 50 LEVEL = GND, RLOAD = 75 ILOS = -30A ILOS = +1.2mA Outputs AC-coupled f < 2MHz CAZ = open CAZ = 0.1F 85 20 20 2 2 100 50 115 76 550 1100 2.4 0.450 1270 IN+ to IN(Notes 2, 3) (Notes 2, 4) (Note 6) (Notes 2, 7) (Notes 7, 8) RTH = 2.5k RTH = 2.5k RTH = 7k RTH = 7k RTH = 20k RTH = 20k 0 97 18.0 9.9 2.20 2.2 10 11 8 100 4.4 1 4.8 8.5 16 27 41.5 67 80 100 230 1200 1800 111 400 103 43.0 13.6 155 CONDITIONS MIN TYP 2.5 1200 25 MAX UNITS Gbps mV psp-p psRMS ps dB s mV mV mV mV mV mV A VRMS mV V V mV dB MHz kHz mA
Note 1: Specifications for Input Voltage Range, LOS Assert/Deassert Levels, and CML Output Voltage refer to the total differential peak-to-peak signal applied or measured. PECL output voltages are absolute (single-ended) voltages measured at a single output. Note 2: Input edge speed is controlled using four-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum data rate. Note 3: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A. Note 4: Random jitter is measured with the minimum input signal applied after filtering with a four-pole, lowpass, Bessel filter (frequency bandwidth at 75% of the maximum data rate). For Fibre Channel and Gigabit Ethernet applications, the peak-topeak random jitter is 14.1-times the RMS random jitter. Note 5: Input signal applied after a 933MHz Bessel filter. Note 6: Input signal applied after a 1.8GHz Bessel filter. Note 7: Input for LOS assert/deassert and hysteresis tests is a repeating K28.5 pattern. Hysteresis is defined as: 20log (VLOS-DEASSERT / VLOS-ASSERT). Note 8: Response time to a 10dB change in input power. 4 _______________________________________________________________________________________
+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX3264/5/8/9 TOC01a
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
MAX3264 LOS HYSTERESIS vs. TEMPERATURE
MAX3264/5/8/9 TOC03a
MAX3265EUE LOS HYSTERESIS vs. TEMPERATURE
MAX3264/5/8/9 TOC03
1700 1500 OUTPUT VOLTAGE (mV) MAX3264/MAX3268 1300 1100 900 700 500 300 0 2 4 6 8 10 MAX3265/MAX3269/MAX3765
6.5 6.0 LOS HYSTERESIS (dB) 5.5 5.0 RTH = 7k 4.5 4.0 3.5 RTH = 25k
6.5 6.0 LOS HYSTERESIS (dB) 5.5 5.0 4.5 4.0 3.5 RTH = 16k RTH = 4.6k
12
0
10
20
30
40
50
60
70
-40
-15
10
35
60
85
INPUT VOLTAGE (mV)
TEMPERATURE (C)
TEMPERATURE (C)
MAX3264/MAX3268/MAX3768 DETERMINISTIC JITTER vs. INPUT AMPLITUDE
MAX3264/5/8/9 TOC04
MAX3264/MAX3268/MAX3768 RANDOM JITTER vs. INPUT AMPLITUDE
14 12 RMS JITTER (ps) 10 8 6 4
MAX3264/5/8/9 TOC05
MAX3265/MAX3269/MAX3765 DETERMINISTIC JITTER vs. INPUT AMPLITUDE
MAX3264/5/8/9 TOC06
30 25 20 JITTER (ps) 15 10 5 0 0 200 400 600 800 1000
16
30 25 20 JITTER (ps) 15 10 5 0
2 0 1200 0 10 20 30 40 50 INPUT AMPLITUDE (mV) INPUT AMPLITUDE (mV)
0
200
400
600
800
1000
1200
INPUT AMPLITUDE (mV)
MAX3265/MAX3269/MAX3765 RANDOM JITTER vs. INPUT AMPLITUDE
MAX3264/5/8/9 TOC07
LOSS OF SIGNAL WITH SQUELCH
VIN
MAX3264/5/8/9 TOC08
MAX3268/MAX3768 DATA OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3264/5/8/9 TOC09
8 7 6 RMS JITTER (ps) 5 4 3 2 1 0 0 10 20 30 40
VOUT 300mV/div
VLOS
50
500ns/div
200ps/div
INPUT AMPLITUDE (mV)
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX3264 DATA OUTPUT EYE DIAGRAM AT 1.25Gbps (MINIMUM INPUT)
MAX3264/5/8/9 TOC10
MAX3264 DATA OUTPUT EYE DIAGRAM AT 1.25Gbps (MAXIMUM INPUT)
MAX3264/5/8/9 TOC11
MAX3265/MAX3765 DATA OUTPUT EYE DIAGRAM 2.5Gbps (MINIMUM INPUT)
MAX3264/5/8/9 TOC12
150mV/div
50mV/div
150mV/div
200ps/div
200ps/div
100ps/div
MAX3265/MAX3765 DATA OUTPUT EYE DIAGRAM 2.5Gbps (MAXIMUM INPUT)
MAX3264/5/8/9 TOC13
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
25 20 PSRR (dB) 15 10 5 0
MAX3264/5/8/9 TOC14
OUTPUT VSWR vs. FREQUENCY
MAX3264/5/8/9 TOC15
4.0 3.5 3.0 VSWR 2.5 2.0 1.5 1.0
150mV/div
100ps/div
100k
1M
10M FREQUENCY (Hz)
100M
1G
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
MAX3264 LOSS-OF-SIGNAL THRESHOLD vs. RTH
MAX3264/5/8/9 TOC18
MAX3265/MAX3765 LOSS-OF-SIGNAL THRESHOLD vs. RTH
MAX3264/5/8/9 TOC19
COMMON-MODE REJECTION RATIO vs. FREQUENCY
50 45 40 CMRR (dB) 35 30 25 20 15 10 MAX3265/MAX3765 MAX3268/MAX3768
MAX3264/5/8/9 TOC20
40 35 LOS ASSERT THRESHOLD (mV) 30 25 20 15 10 5 0 0 5 10 15 20 RTH (k) 25 30
60 50 40 30 20 10 0
55
LOS ASSERT THRESHOLD (mV)
5 0 5 10 15 RTH (k) 20 25 30 1M 10M 100M FREQUENCY (Hz) 1G 10G
35
6
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Pin Description
PIN NAME MAX 1, 4 2 3 5 TSSOP 3, 6 4 5 8 GND IN+ INTH Supply Ground Noninverted Input Signal Inverted Input Signal Loss-of-Signal Threshold. A resistor connected from this pin to ground sets the input signal level at which the loss-of-signal (LOS) output(s) is asserted. Refer to Typical Operating Characteristics and Design Procedure. Inverted Loss-of-Signal Output. LOS is high when the level of the input signal is above the preset threshold set by the TH input. LOS is asserted low when the signal level drops below the threshold. Supply Voltage Inverted Data Output Noninverted Data Output Offset-Correction-Loop Capacitor. A capacitor connected between this pin and CAZ2 extends the time constant of the offset correction loop. Offset-Correction-Loop Capacitor. A capacitor connected between this pin and CAZ1 extends the time constant of the offset correction loop. Refer to Design Procedure. Output Current Level. When this pin is not connected, the CML output current is approximately 16mA. When this pin is connected to ground, the output current increases to approximately 20mA. (In the MAX3265CUB/MAX3765CUB, LEVEL is internally connected to ground.) Noninverted Loss-of-Signal Output. LOS is low when the level of the input signal is above the preset threshold set by the TH input. LOS asserts high when the signal level drops below the threshold. Squelch Input. The squelch function is disabled when SQUELCH is not connected or is set to a TTL low level. When SQUELCH is set to a TTL high level and LOS is asserted, the data outputs, OUT+, and OUT-, are forced to static levels. See sections PECL Output Buffer and CML Output Buffer for more information. (In the MAX3265/MAX3268/MAX3269 10-pin MAX, SQUELCH is not connected. In the MAX3765/MAX3768, SQUELCH is internally connected to VCC.) No Connection Ground. The exposed paddle must be soldered to the circuit-board ground for proper thermal performance. FUNCTION
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
6 7, 10 8 9 --
9 11, 14 12 13 1
LOS VCC OUTOUT+ CAZ1
--
2
CAZ2
--
7
LEVEL
--
10
LOS
--
15
SQUELCH
-- EP
16 EP
N.C. Exposed Paddle
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
VCC VCC VCC VCC 100 100 100 RTERM 100 COUT 2 x RLOAD 100 100 100 300 RTERM 300 COUT 2 x RLOAD 150
COUT
COUT
MAX3264 MAX3265 MAX3765 (a) MAX3264/MAX3265/MAX3765 WITH 50 TERMINATION
MAX3264 MAX3265 MAX3765 (b) MAX3264/MAX3265/MAX3765 WITH 75 TERMINATION VCC
MAX3268 MAX3269 MAX3768
OUTOUT+
50
RTERM 50
(c) MAX3268/MAX3269/MAX3768 OUTPUT TERMINATION
VCC - 2V
Figure 1. Data Output Termination
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
VCC
ICC IOUT 100 100
MAX3264CUE: OPEN MAX3265CUE: OPEN SQUELCH MAX3265CUB: GND (INTERNAL) MAX3765CUB: VCC (INTERNAL) MAX3264 MAX3265 MAX3765 CONTROL LEVEL MAX3264CUE: OPEN MAX3265CUE: OPEN MAX3265CUB: GND (INTERNAL) MAX3765CUB: GND (INTERNAL)
RTH 2.5k
(a) CML SUPPLY CURRENT (ICC)
VCC
ICC
OUT+
OPEN
MAX3268 MAX3269 MAX3768 RTH 2.5k
OUTOPEN
(b) PECL SUPPLY CURRENT (ICC)
Figure 2. Power-Supply Current Measurement _______________________________________________________________________________________ 9
+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
_______________Detailed Description
Figure 3 is a functional diagram of the MAX3264/ MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 limiting amplifiers. A linear input buffer drives a multistage limiting amplifier and an RMS power-detection circuit. Offset correction with lowpass filtering ensures low deterministic jitter. The output buffer produces a limited output signal. The MAX3264/MAX3265/MAX3765 produce a CML output, while the MAX3268/MAX3269/ MAX3768 produce a PECL-compatible output signal. Schematics of these input/output circuits are shown in Figures 4 through 7.
RMS Power Detect with Loss-of-Signal Indicator
An RMS power detector looks at the signal from the input buffer and compares it to a threshold set by the TH resistor (see Typical Operating Characteristics for appropriate resistor values). The signal-detect information is provided to the LOS outputs, which are internally terminated with 8k (MAX3265/MAX3269/MAX3765) or 16k (MAX3264/MAX3268/MAX3768) pullup resistors. The LOS outputs meet TTL voltage specifications when loaded with a resistor 4.7k.
TH VCC
MAX3264 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768
RLOS = 8k (MAX3265/MAX3269/MAX3765) RLOS = 16k (MAX3264/MAX3268/MAX3768) RLOS TTL POWER DETECT WITH COMPARATOR TTL VCC LOS
RLOS LOS
IN+ 100 ININPUT BUFFER
GAIN OUT+ OUTPUT BUFFER OUT-
SQUELCH LOWPASS OFFSET CORRECTION 100pF CONTROL LEVEL
CAZ1 TOTAL GAIN = 55dB (MAX3264/MAX3268/MAX3768) TOTAL GAIN = 49dB (MAX3265/MAX3269/MAX3765)
CAZ2
Figure 3. Functional Diagram
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Input Buffer
The input buffer is designed to accept input signals from the MAX3266/MAX3267 transimpedance amplifiers. The input buffer provides a 100 input impedance between IN+ and IN-. Input VSWR is typically less than 2.0 for frequencies less than 2GHz. DC-coupling the inputs is not recommended; this prevents the DC offset-correction circuitry from functioning properly.
CML Output Buffer
The MAX3264/MAX3265/MAX3765 CML output circuits (Figure 7) provide high tolerance to impedance mismatches and inductive connectors. The output current can be set to two levels. When the LEVEL pin is left unconnected, output current is approximately 16mA. Connecting LEVEL to ground sets the output current to approximately 20mA. The squelch function is enabled when the SQUELCH pin is set to a TTL-high level or connected to VCC. The squelch function holds OUT+ and OUT- at a static voltage whenever the input signal power drops below the loss-of-signal threshold. In the 10-pin MAX package of the MAX3265/MAX3268/MAX3269, the SQUELCH function is left internally unconnected. In the MAX3765/ MAX3768, the SQUELCH function is always enabled by internally connecting it to VCC. SQUELCH operation for the MAX3264/MAX3265 is described in Table 1.
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
Gain Stage and Offset Correction
The limiting amplifier provides approximately 55dB (MAX3264/MAX3268/MAX3768) or 49dB (MAX3265/ MAX3269/MAX3765) of gain. This large gain makes the amplifier susceptible to small DC offsets in the input signal. DC offsets as low as 1mV reduce the accuracy of the power-detection circuit and may cause deterministic jitter. A low-frequency feedback loop is integrated into the limiting amplifier to reduce input offset, typically to less than 100V. An external capacitor connected between CAZ1 and CAZ2, in parallel with internal capacitance, determines the time constant of the offset-correction circuit. The offset-correction circuit requires an average data-input mark density of 50% to prevent an increase in dutycycle distortion and to ensure low deterministic jitter.
Table 1. Squelch Operation
LEVEL PIN Open GND VOLTAGE WHEN SQUELCHED OUTVCC - 100mV VCC - 100mV OUT+ VCC VCC - 100mV
Internal Input/Output Schematics
VCC
500 0.25pF IN+ 110 IN0.25pF
500
VCC
RT LOS
ESD STRUCTURES
ESD STRUCTURE
GND RT = 8k (MAX3265/MAX3269/MAX3765) RT = 16k (MAX3264/MAX3268/MAX3768) GND
Figure 4. Input Circuit
Figure 5. LOS Output Circuit 11
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
VCC VCC ESD STRUCTURES ESD STRUCTURES 100 100 OUT+ OUTOUT+ OUT-
GND
GND
LEVEL
Figure 6. PECL Output Circuit
Figure 7. CML Output Circuit
The buffer's output impedance is determined by the parallel combination of internal and external pullup resistors, which are chosen to match the impedance of the transmission line (Figure 1). The output buffer can be AC- or DC-coupled to the load.
minimized when the input low-frequency cutoff (fIN) is placed at a low frequency: fIN = 1 / [2(50)(C)] For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) 0.01F, which provides fIN < 320kHz. For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) 0.1F, which provides fIN < 32kHz.
PECL Output Buffer
The MAX3268/MAX3269/MAX3768 offer an industrystandard PECL output. The PECL outputs should be terminated to VCC - 2V. Figure 6 shows the PECL output circuit. The squelch function forces OUT+ to a high level and OUT- to a low level when the input is below the programmed LOS threshold. In the 10-pin MAX, SQUELCH is left unconnected.
Select the Offset-Correction Capacitor (MAX3264/MAX3265 TSSOP Only)
To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC-offset-correction circuit. fOC = 75 / [2 60k (CAZ + 100pF)] = 200 x 10 -6 / (CAZ + 100pF) For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, leave pins CAZ1, and CAZ2 open (fOC = 2MHz). For ATM/SONET or other applications using scrambled NRZ data, select CAZ 0.1F, which typically provides fOC = 2kHz.
__________________Design Procedure
Program the LOS Assert Threshold
The loss-of-signal threshold is programmed by external resistor RTH. See the LOS Threshold vs. RTH graph in the Typical Operating Characteristics.
Select the Coupling Capacitors
The coupling capacitors (CIN, COUT) should be selected to minimize the receiver's deterministic jitter. Jitter is
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+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Applications Information
Optical Hysteresis
In an optical receiver, the electrical power change at the limiting amplifier is 2x the optical power change. As an example, if a receiver's optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the limiting amplifier also increases by a factor of two. The optical power change is 10log(2x / x) = 10log(2) = +3dB. At the limiting amplifier, the electrical power change is:
10log
VCC_MODULE HOST VCC_HOST
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
GBIC MODULE
4.7k
(2VIN )2 / RIN
VIN2 / RIN
= 10log(22 ) = 20log(2) = + 6dB
MAX3264 MAX3265 MAX3268 LOS MAX3269 MAX3765 MAX3768
GENERALPURPOSE NPN
The MAX3264/MAX3265/MAX3268/MAX3269/MAX3765s' typical voltage hysteresis is 4.4dB. This provides an optical hysteresis of 2.2dB.
Figure 8. Recommended GBIC LOS Circuit
GBIC Loss of Signal
In a GBIC application, the GBIC's LOS output must be high impedance when VCC_MODULE = GND. Figure 8 shows the recommended circuit to maintain high impedance. ESD protection diodes on the MAX3264/ MAX3265/MAX3268/MAX3269/MAX3765/MAX3768 LOS outputs can be turned on when V CC_ HOST > VCC_MODULE.
OUT+ 470
MAX3268 MAX3269 MAX3768
OUT470
50
PECL Terminations
The standard PECL termination (50 to VCC - 2V) is recommended for best performance and output characteristics (see Figure 1). The data outputs operate at high speed and should always drive transmission lines with matched, balanced terminations. Figure 9 shows an alternate method for terminating the data outputs. The technique provides approximately 8mA DC bias current, with a 45 AC load, for the output termination. This technique is useful for viewing the output on an oscilloscope or changing the PECL reference voltage.
50
DRIVING 50 TO GROUND
Figure 9. Alternative PECL Termination
Wire Bonding Dice
For high current density and reliable operation, the MAX3264/MAX3265/MAX3268/MAX3269 use gold metalization. Make connections to the dice with gold wire only, and use ballbonding techniques (wedge bonding is not recommended). Die-pad size is 4 mils square, with a 6-mil pitch. Die thickness is 15 mils (0.375mm).
______________________________________________________________________________________
13
+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
Typical Operating Circuits (continued)
VCC
VCC
CIN 0.01F IN+ 100 IN-
MAX3268CUB MAX3269CUB MAX3768CUB
OUT+
OUT50 TH LOS VCC - 2V SIGNAL DETECT 50
MAX3266 MAX3267
CIN 0.01F
RTH
Pin Configurations
TOP VIEW
CAZ1 1 CAZ2 2 GND 3 IN+ 4 IN- 5 GND 6 LEVEL 7 TH 8 16 N.C. 15 SQUELCH 14 VCC GND 1 IN+ INGND TH 2 3 4 5 10 VCC 9 OUT+ OUTVCC LOS
MAX3264 MAX3265
13 OUT+ 12 OUT11 VCC 10 LOS 9 LOS
MAX3265 MAX3268 MAX3269 MAX3765 MAX3768 MAX
8 7 6
TSSOP
NOTE: EXPOSED PADDLE IS GROUND.
14
______________________________________________________________________________________
+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Selector Guide
PART MAX3264 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768 *LEVEL pin grounded OUTPUT CML CML PECL PECL CML PECL DATA RATE (Gbps) 1.25 2.5 1.25 2.5 2.5 1.25 PINPACKAGE 16 TSSOP-EP 16 TSSOP-EP 10 MAX-EP 10 MAX-EP 10 MAX-EP 10 MAX-EP 10 MAX-EP SQUELCH FUNCTION Selectable Selectable Disabled Disabled Disabled Enabled Enabled CML OUTPUT LEVEL Selectable Selectable Maximum* N/A N/A Maximum* N/A
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
Chip Topographies
MAX3264/MAX3265/MAX3765
CAZ1 N.C.
MAX3268/MAX3269/MAX3768
CAZ1 N.C.
CAZ2 GND IN+ INGND LEVEL
SQUELCH VCC OUT+ OUTVCC LOS 0.061" (1.55mm)
CAZ2 GND IN+ INGND
SQUELCH VCC OUT+ OUTVCC LOS 0.061" (1.55mm)
TH
N.C. 0.061" (1.55mm)
LOS
TH
N.C. 0.061" (1.55mm)
LOS
MAX3264/MAX3265/MAX3765 TRANSISTOR COUNT: 726 MAX3268/MAX3269/MAX3768 TRANSISTOR COUNT: 728 SUBSTRATE CONNECTED TO GND
______________________________________________________________________________________
15
+3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
16
______________________________________________________________________________________
3.0V to 5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
48L TSSOP.EPS
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765
321
E
H
N
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
b A1 A2 e D
SEATING PLANE
;
A
C L
c b
SIDE VIEW
END VIEW
WITH PLATING
b1
(;
)
PARTING LINE BASE METAL
c1
c
0.25
DETAIL A
SECTION C-C
NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE. 3. CONTROLLING DIMENSION: MILLIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED. 5. "N" REFERS TO NUMBER OF LEADS. 6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 48L TSSOP, 6.1mm BODY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0155
1 2
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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